PAM4 Gigabit Ethernet Electrical SERDES Analysis, Debug and Compliance Testing

This white paper shows how the introduction of complicated figures of merit like SNDR, COM, and ERL, plus FEC (forward error correction) changes how we think about SERDES performance. SERDES tests require more than pristine signal generation and error counting. This paper presents the key SERDES tests, the need for FEC test patterns and the ability to insert errors that can probe Reed-Solomon FEC, and techniques for calibrating interference and jitter tolerance tests.

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